The SOG (system on glass) technology can be actualized by technologies of a-Si and LTPS (low temperature poly-silicon). The major difference between a LTPS TFT and an a-Si TFT is the complexity of manufacturing process and the electrical characteristics. A LTPS TFT has a higher carrier-mobility whereas its manufacturing process is more complicated. By contrast, a-Si TFT has a lower carrier-mobility than LTPS, but its manufacturing process is simpler and well developed, and therefore an a-Si TFT has a better competitiveness in terms of cost.
Accordingly, due to the limit of manufacturing ability, the threshold voltage (Vth) for the manufactured a-Si TFT elements that follows the affection of the applied stress increases gradually. This is the important reason why a SOG cannot be actualized by an a-Si TFT. Therefore, overcoming the meta-stability of the Vth resulting from the manufacturing process so as to actualize the SOG by an a-Si TFT manufacturing process is the problem that to be solved urgently now.
Please refer to FIGS. 1 and 2 that are a schematic diagram and the timing diagram for the shift register circuit disclosed in Prior Art U.S. Pat. No. 5,222,082 entitled “Shift Register Useful as a Select Line Scanner for Liquid Crystal Display”. As shown in FIG. 1, the circuit is composed of six TFTs, where TFT T5 is used to offer a high-level logic voltage to the output terminal Vout while TFT T6 is used to offer a low-level logic voltage to the output terminal Vout. The activities are described as follows. TFT T1 and T4 are turned on when the output voltage of the next-former stage g(i−1) is at a logic high voltage level. At this moment, the voltage level of node P1 is pulled up to high-level supply voltage Vdd because of the active TFT T1. TFT T5 is turned on when the voltage level of node P1 is higher than the Vth of TFT T5. The clock-pulse signal C1 is at a logic low voltage level at this time such that the output voltage Vout is pulled down to logic low voltage level via the discharging circuit formed by TFT T5. At the same time when TFT T4 is active, TFT T3 is also turned on because the output voltage of the next-former stage g(i−1) and the clock-pulse signal C3 are in-phase. For the purpose of smoothly discharging from the clock-pulse signal C1 to the output terminal Vout, the element dimension of T4 should be 10 times larger than T3's in order to lower the voltage level of node P2 so that circuit mis-action caused by active TFT T2 and TFT T6 can be avoided.
When the clock-pulse signal C1 rises from logic low voltage level to logic high voltage level, the voltage level of node P1 will rise from supply voltage Vdd to a higher level that is affected by the parasitic capacitance Cgs of TFT T5. This is so called bootstrap effect. This effect lets the clock-pulse signal C1 output more easily.
When the clock-pulse signal C1 goes back to logic low voltage level again from logic high voltage level, the voltage level of node P1 is still high. Until the clock-pulse signal C3 returns to logic high voltage level again, the voltage level of node P1 returns to logic low voltage level from logic high. As a result, the output voltage Vout is pulled down to logic low voltage level due to TFT T5 is turned on.
When the clock-pulse signal C3 returns to logic high voltage level again, the output voltage of the next-former stage g(i−1) is at a logic low level at this moment. Accordingly, TFT T4 is turned off and the voltage level of node P2 is pulled up to a high level as supply voltage Vdd due to TFT T3 is turned on. Due to the high-level voltage Vdd of node P2 turns on TFT T2 and TFT T6, both the voltage levels of node P1 and the output Vout will be pulled down to low-level supply voltage Vss. Until the next frame arrives, the output voltage of the next-former stage g(i−1) is pulled up to logic high voltage level again, the voltage levels of node P1 and the output Vout will be respectively pulled up to supply voltage Vdd and logic high voltage level again due to TFT T1 and T5 are turned on.
The defect of Prior Art U.S. Pat. No. 5,222,082 is that the whole shift register circuit needs three clock-pulse signals to complete the function. Moreover, nodes P1 and P2 of the circuit will be in a floating state for a short time, which results in circuit mis-actions due to nodes P1 and P2 are affected by clock-pulse signal or other noises. Besides, threshold voltages (Vth) for TFT T2, T3, and T6 increase because of the sustained stress, which leads to the circuit fails at last.
Further, please refer to FIGS. 3 and 4 that are the schematic diagram and the timing diagram for the shift register circuit disclosed in U.S. Pat. No. 3,937,984 entitled “Shift Register”. The circuit is composed of three TFTs and one capacitor C, where TFT T2 is used to offer a high-level logic voltage to the output terminal Vout while TFT T3 is used to offer a low-level logic voltage to the output terminal Vout. TFT T1 is turned on when both the clock-pulse signal C1 and the output voltage of the next-former stage g(i−1) are at a logic high voltage level. At this moment, the voltage level of node P1 is pulled up to logic high voltage level via the charging circuit formed by TFT T1. TFT T2 is turned on when the voltage level of node P1 is higher than the Vth of TFT T2. The clock-pulse signal C2 is at a logic low voltage level at this time such that the output voltage Vout is pulled down to logic low voltage level via the discharging circuit formed by TFT T2.
When the clock-pulse signal C2 rises from logic low voltage level to logic high voltage level, the voltage level of node P1 will rise to a higher level that is affected by the parasitic capacitance Cgs of TFT T2, which is the bootstrap effect. This effect lets the clock-pulse signal C2, which is at a logic high voltage level now, output more easily. When the clock-pulse signal C2 goes back to logic low voltage level again from logic high voltage level, the clock-pulse signal C1 is at a logic high voltage level at this time such that the voltage level of node P1 is pulled down to logic low voltage level via the discharging circuit formed by TFT T1 and TFT T2 is turned off. At this moment, the control voltage Vc1 continuously supplies a logic high voltage to the gate of TFT T3, which keeps the output voltage Vout at low-level supply voltage Vss. Until the next frame arrives, the output voltage of the next-former stage g(i−1) is pulled up to logic high voltage level again, the voltage levels of node P1 and the output Vout will be pulled up to logic high voltage level again due to TFT T1 and T2 are turned on.
However, in the shift register circuit of the U.S. Pat. No. 3,937,984, node P1 will be in a floating state for a short time, which results in the circuit mis-action of TFT turn-on due to nodes P1 is affected by clock-pulse signal or other noises. Besides, threshold voltages (Vth) for TFT T1 and T3 increase because of the sustained stress, which leads to the circuit fails at last.